Serial digital video transmitter for HD video surveillance and HDcctv applications
Dual rate operation 270Mbps and 1.485Gbps
Backward compatible with HDcctv 1.0 and HDSDI (ST 292)
Integrated High Definition Visually Lossless CODEC (HDVLC™) for extended cable reach
500m over 755 (5C) CCTV coax
300m over 753 (3C) CCTV coax
150m over Cat5e/6 UTP cable
Configurable 50/75ohm cable driver output, for both coaxial and twisted pair cable transmission
Integrated audio embedder with support for up to 4 channels of I2S serial digital audio at 32kHz, 44.1kHz and 48kHz sample rates
Downstream ancillary data insertion
Supports both 720p and 1080p HD formats
1080p 25/29.97/30fps
720p 25/29.97/30/50/59.94/60fps
Tissu 100% COTON chame & tram e Retors, arm ure toile 1/1, 390g/m2, 140cm, huile
Principales utilisations vetem ents de pluie
Principales utilisations:vetements de pluie
The GS2971A is a multirate SDI integrated Receiver which includes complete SMPTE processing, as per SMPTE 425M, 292M and SMPTE 259MC. The SMPTE processing features can be bypassed to support signals with other coding schemes.
The GS2971A integrates Gennum's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTE pathological signals.
The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI.
A serial digital loopthrough output is provided, which can be configured to output either reclocked or nonreclocked serial digital data. The serial digital output can be connected to an external cable driver.
The device operates in one of four basic modes SMPTE mode, DVBASI mode, DataThrough mode or Standby mode.
The EP103T LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 25 bits (8bits/color, 2 dummy bits) of Low Voltage TTL data and 3 control bits into 4 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 3.78Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin. Support 10MHz to 135MHz clock rates for
HVGA to SXGA+ resolution
Up to 3.78Gbps bandwidth
PLL requires no external components
Cycletocycle jitter rejection
3.3V to 1.8V Low Voltage TTL tolerant Input
Programmable data and control strobe select
Power down mode supported